U.S. Pat. No. 5,843,812 describes a manufacturing process of a p-MOSFET having a polysilicon gate wherein a BF2 ion implantation is performed into said polysilicon gate in order to achieve a more stable threshold voltage.
Although in principle applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated memory circuits in silicon technology.
To improve the speed of the periphery devices, the device length as well as a gate oxide thickness have to be scaled down. Below a certain thickness of 2 nm, the gate leakage is very important and increases exponentially. High-k dielectrics are supposed to improve the gate oxide problem. However, the integration of the high-k dielectric together with a N+ polysilicon gate is very difficult due to the fermi-level pinning.
Also, gate polysilicon depletion is becoming a limiting factor for on-current of small gate-length transistors with a thin gate dielectric having a thickness of less than about 2 nm. The gate poly-depletion effect usually contributes to a 7–10×10−10 m (Ångström) increase of the overall effective oxide thickness of the gate dielectric for logic devices. The gate polysilicon depletion is even more severe for p-MOSFETs in DRAM support devices due to the higher boron deactivation during DRAM processing.
Metal gates which are free from poly-depletion effects have been anticipated for replacement of polysilicon gates. However, issues such as a process compatibility, device reliability and difficulties in integrating dual work-function metal gates for both p- and n-MOSFETs have hindered the introduction of metal gates. Though p-MOSFETs with an N+ polysilicon gate are also free from polysilicon depletion effect, the threshold voltage will be too high for any practical application due to the improper work-function of the N+ polysilicon.